Demands for high-speed data processing and communication continue to push the electronics industry to develop faster and higher-functioning circuits, as has been realized in very-large-scale integration of circuits on small areas of silicon wafer. Technologies such as telecommunications and networking, for example, continue to fuel research and design efforts that facilitate serial data rate capabilities on the order of hundreds of gigabits per second and higher.
Such data-processing speeds are defined relative to a clock source that provides one or more high-frequency signals to circuits (and/or functionally-defined circuit modules) that advance through their designed (logic) states in order to perform their designed operation. In a typical application, the clock source provides a high-frequency signal that is processed through divider circuits to generate and distribute the appropriate clock signals to the various modules so as to advance through their logic states at the appropriate rate. In this manner, the high-speed clock source permits such circuitry to achieve its high-speed data-processing operation.
The distribution of these clock signals in a typical high-speed data processing application requires careful management of the circuits that generate these clock signals to operational and data-integrity problems. In circuits operating at relatively high clock speeds, for example, in the 1 GHz area and certainly at frequencies above about 5 GHz, such management is especially important.
At such high clock speeds, signal distortion can be caused by a form of noise known as clock jitter and by common-mode voltage problems. Clock jitter refers to the deviation in a clock signal's actual transition in time from its ideal position in time, where the signal's actual transition may either lag or lead the ideal position in time. Clock jitter includes cycle-to-cycle jitter, which is the change in a signal's output transition from its corresponding position in the previous cycle, as well as period jitter, which is the maximum change in a signal's output transition from its ideal position. Since both forms of jitter are present in high-frequency clocks, the circuit designer attempting to achieve a maximum data rate would typically need to account for the short-term and long-term (accumulation of such jitter over time) effects of clock jitter.
At these higher clock speeds, the clock source is typically an analog circuit producing an analog signal that must interface with digital circuitry before a useful digital clock signal can be produced. The common-mode voltage carried by this analog signal presents additional potential for distortion that can also be carried through the system. Clock sources that oscillate at such high frequencies are typically designed to provide differential analog signals that oscillate in a narrow voltage range below the upper power supply rail, Vdd, and a high-impedance analog buffer is used to amplify this analog signal with sufficient swing for an input of a typical digital circuit. However, this amplified analog signal is also differential and it is carried by a common-mode DC voltage that is not centered between the upper and lower power supply rails, Vdd and VSS. Consequently, the typical amplification provided by the typical digital circuit over-amplifies the signal on one voltage swing and under-amplifies the signal on the opposite voltage swing. For example, where the digital circuit is an inverter, the inverter would over-amplify the signal's valleys and under-amplify the signal's peaks. The digital circuit therefore fails to recognize half of the input states presented at its digital input, and modules depending on this signal would not recognize the clock transitions and fail to advance at the correct times.
In situations where jitter is combined with this common-mode voltage problem, this distortion can adversely impact even less-sensitive circuits. These situations can arise when the clock signal swing is barely within an acceptable range relative to supply rails, and then clock jitter is introduced to the clock signal. In such situations, the clock-driven modules can improperly interpret clock transitions in the clock signal. In other instances and operating conditions, clock jitter can have the effect of momentarily negating the swing in the clock signal. Under theses scenarios, the intended clock transitions would not be recognized and therefore not cause the clock-drive modules to advance their respective logic states.
Various approaches have been used to manage these conditions and eliminate this concern. A typical approach, for example, has involved use of a conventional R-C (resistor-capacitor) filter and an operational amplifier. The clock signal passes through the R-C filter to provide a level-averaged signal to the operational amplifier. The operational amplifier then compares this level-averaged signal against a reference voltage. The operational amplifier is configured with a feedback circuit to adjust the common-mode voltage. While this type of approach is acceptable for many applications, many other applications must address ongoing demands for decreased circuit size and decreased component-count.
Another approach is to use circuitry that is specially designed to compensate for otherwise intolerable swing levels in the clock signal. With the above-discussed digital inverter example, this approach would involve adjusting the size of the inverter to compensate for the high common-mode voltage provided at the output of the analog buffer. However, because this size adjustment is particular to one operating environment (as defined, e.g., by processing, voltage and temperature operation specifications), this approach will work only for that particular environment.
Accordingly, an approach that addresses the aforementioned problems, as well as other related problems, is desirable.